Storage Class Memories, SCM, are nonvolatile storage technologies using low cost materials such as chalcogenides, perovskites, phase change materials, or magnetic bubble technologies. Storage class memories exhibit DRAM-like performance at lower cost than DRAM. The extrapolated cost over time can be equivalent to or less than that of enterprise class disk drives. The cost performance of the storage class memories provides a level in the storage hierarchy between the DRAM main system memory and disk storage. This level of storage may be viewed as a very large disk cache in which data can be stored permanently due to the nonvolatile characteristics of storage class memories.
Many storage class memory technologies are physical block addressed; i.e., unlike DRAM, a block of data is read or written. The physical block sizes typically range from 512 bytes to 4K bytes. Hence, storage class memory is suitable as a replacement for block access disk drives.
However, unlike DRAM and disk drives, storage class memory technologies provide a finite number of write cycles. Flash memories also exhibit this characteristic. While flash memories provide 106 to 108 write cycles, storage class memory technologies support 1010 to 1012 write cycles. To optimize the life of a storage device, data are written so that the storage medium is used in a uniform manner even if the write accesses are skewed to use a small set of addresses. The physical device space is divided into physical blocks that are written and read. The number of write cycles is tracked for each physical block so that when a physical block is updated, the data in the physical block (further referenced as a block of data or data) may be written to another physical block with lower wear. Distributing the written block of data to level the write operations prevents the loss of the device due to wear in a subset of physical block address that has frequent updates.
Flash memories use algorithms and file management structures to level the wear in the device. These differ from the storage class memory technologies in that flash memories require data be written into a physical block that has been erased. The erase process takes significant time compared to the read and write cycle time. Flash memories are organized with erase zones containing multiple physical blocks to enable the erasing of a number of physical blocks in parallel so that physical blocks are available for updating physical blocks of data. Thus, in a flash memory, the data moves with each update. Journal file structures have been used for wear leveling; tracking the wear level for each physical block is not required since all physical blocks are uniformly written. While providing even wear, many journal file mechanisms move a significant portion of the data and are actually a major cause of wear. Further, a time delay of milliseconds may be required to erase the physical blocks prior to updating. While useful for current applications, this time delay is unacceptable for most system memory applications.
In contrast to memory management of flash memories, storage class memory technologies provide an update in place capability so data need not be moved for update. A conventional wear leveling mechanism used by storage class memory technologies prolongs the life of the storage class memory device and requires additional data structures and overhead in accessing the physical blocks compared to direct physical block addressing.
A conventional wear leveling mechanism comprises an address translation system and a method for tracking physical block wear and for identifying physical blocks with low usage. Although this technology has proven to be useful, it would be desirable to present additional improvements.
The address translation system uses an address to access a block of data stored in a physical block of memory; the address translation system expects that the address used to access the data is constant independent of the physical block in which the data is stored. The storage class memory device provides a mapping of the system address for a block of data to the physical location of the physical block. When a block of data is accessed, the address translation identifies the physical block. For rapid address translation, an index structure or hash tables may be constructed. When a block of data is written to another physical block location, the map is changed to reflect the address of the newly written physical block. For a hashed or indexed translation table, the hash tables or indices are also changed. However, changing location of the data to another physical block requires address translation updating overhead.
A file system may provide the address translation; in this case the file system directories are updated when a block of data is written in a physical block of lower wear rather than the original physical block for the data.
Conventional storage class memory systems comprise a method for tracking wear of a physical block such that the number of write cycles for each physical block is tracked. For each write operation that requires the data to be moved for even wear, a physical block with a low wear level is identified and used.
One conventional mechanism for identification of empty physical blocks with low wear is an ordered list of physical blocks. The physical block at the end of the list has the lowest wear level. When the physical block with lowest wear is used, the wear level is incremented and the physical block is removed from the list. When the physical block is updated, the data in the physical block is moved to the physical block with least wear and the previously used physical block is inserted into the empty physical block list to maintain the ordered list. This conventional approach is useful for small devices. However, large devices pose a significant problem in maintaining the ordered list. For a device of 10 million physical blocks, the list requires a double linked list in which each link can address 10 million elements. An index structure can be defined for ease of insertion; the index can point to the boundaries between physical blocks with the same count. However, the number of wear level values can be very large since these technologies provide 1010 to 1012 write cycles.
Conventional storage class memory systems further comprise a method for identifying physical blocks with low usage. Some of the physical blocks are written infrequently or contain read-only data. These physical blocks have very low wear levels compared to physical blocks that have an average number of updates. If the percentage of physical blocks with infrequent write activity is low, having physical blocks with low usage does not affect the maximum lifetime of the storage class memory. However, if the percentage of physical blocks with infrequent write activity is significant, the remaining physical blocks experience significant wear compared to the physical blocks with infrequent write activity. For example, if 33% of the physical blocks in a storage class memory device are physical blocks with infrequent write activity, then the other 66% of the storage class memory device experiences 150% of the wear. Consequently, the life of the storage class memory device is 66% of a similar storage class memory device with even wear on most of the physical blocks.
What is therefore needed is a system, a computer program product, and an associated method for updating a memory to maintain even wear. A system is further needed to minimize overhead by minimizing a frequency of physical block moves and address table updates required to level wear on the memory. The need for such a solution has heretofore remained unsatisfied.